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Vertical 03Hardware

Hardware & Semiconductor Engineering

Write semiconductor-grade SystemVerilog. Build the memory controllers other people read about.

SystemVerilogRTLVLSIECC

The Hardware vertical is for the 0.1% of builders who want to go deep on RTL design. You will build an HBM-style memory controller from scratch in SystemVerilog: address mapper, command scheduler, bank state machines, ECC, power manager, and refresh engine. You learn the timing constraints nobody explains in textbooks, how to debug with Verilator, and why random stimulus finds bugs directed tests never will.

What You'll Learn

Design a multi-channel DRAM controller with bank-level parallelism

Implement SECDED ECC at the bank level with correctable/uncorrectable error handling

Build a command scheduler that respects 20+ timing constraints simultaneously

Handle refresh, power-down, and self-refresh without data loss

Debug synchronous logic with assertion-based scoreboarding

Run random-stimulus testing that catches bugs directed tests miss

Curriculum

Every module below is free to read and follow — the code, the templates, the receipts. Pro ($29/mo) is for the monthly live Q&A and the private community. Builder ($499/mo) adds direct email access and small-group coaching.

MODULE 01·4h

SystemVerilog Fundamentals

Modules, always blocks, synthesis vs simulation semantics, common pitfalls.

MODULE 02·3h

Memory Architecture

DDR vs HBM, banks, channels, rows, columns, timing parameters explained.

MODULE 03·4h

Command Scheduler

Request queue, bank tracking, reorder logic, stall minimization.

MODULE 04·3h

ECC & Data Path

Hamming codes, SECDED implementation, error reporting, recovery.

MODULE 05·2h

Power & Refresh

Power states, transition timing, refresh scheduling, thermal considerations.

MODULE 06·3h

Verification

Verilator setup, assertions, scoreboards, random stimulus harness.

The Stack

SystemVerilogVerilatorGTKWaveCocotbIcarusVCS

Case Study

Live Build

HBM Memory Subsystem

4,500-line SystemVerilog HBM-style controller. Runs in Verilator, passes directed + random stimulus tests, models multi-channel bank parallelism with ECC and power states.

4,500 lines of production-style SystemVerilog

3 critical bugs caught by random stimulus (missed by directed tests)

10× bandwidth difference between lazy and optimal scheduler

Full refresh timing validation under burst traffic

The modules are free. Pro is for the monthly live Q&A and the community. Builder adds direct access and coaching.

Join Pro — Live Q&A + Community